Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation
Chia-Ling Chen1, Vinay Agarwal2, Sameer Sonkusale2 and Mehmet R. Dokmeci1 Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA Department of Electrical and Computer Engineering, Tufts University, Medford, MA, USA
This paper presents heterogeneous integration of Single-Walled Carbon Nanotubes (SWNTs) with CMOS integrated circuits using die-level post processing. The chip was fabricated using the AMI 0.5μm CMOS Technology. An electroless zincation process was performed over the Aluminum assembly electrodes (Metal 3 of CMOS technology) to clean and to coat the electrodes with a thin Zinc layer. Low temperature dielectrophoretic assembly was utilized for the placement of the SWNTs on to these electrodes. Encapsulating the CMOS chip with a thin (1μm) parylene-C layer stabilized the SWNT-electrode contact resistance and also provided environmental protection. Electrical measurements from the assembled SWNTs yield ohmic behavior with a two-terminal resistance of ~44KΩ. The SWNTs were incorporated on to the CMOS chip as a feedback element of a two-stage Miller compensated high gain operational amplifier.
The measured small signal ac gain (~1.95) from the inverting amplifier confirmed the successful integration of carbon nanotubes with the CMOS circuitry. This paper lays the foundation for the realization of next generation integrated nanosystems with active nanostructures on CMOS integrated circuits.
ALL ABOUT PARYLENE